Apparatus for communication across a capacitively coupled channel

ABSTRACT

Apparatus for communication across a capacitively coupled channel are disclosed herein. An example circuit includes a first plate substantially parallel to a substrate, thereby forming a first capacitance intermediate the first plate and the substrate. A second plate is substantially parallel to the substrate and the first plate, the first plate intermediate the substrate and the second plate. A third plate is substantially parallel to the substrate, thereby forming a second capacitance intermediate the third plate and the substrate. A fourth plate is substantially parallel to the substrate and the third plate, the third plate intermediate the substrate and the fourth plate. An inductor is connected to the first plate and the third plate, the inductor to, in combination with the first capacitance and the second capacitance, form an LC amplifier.

FIELD OF THE DISCLOSURE

This disclosure relates generally to electronic communications, and, more particularly, to apparatus for communication across a capacitively coupled channel.

BACKGROUND

Electronic communications systems often need to communicate data from a first circuit operating in a first voltage domain to a second circuit operating in a second voltage domain. In some examples, the first voltage domain may be on the order of one hundred volts, whereas the second voltage domain may be on the order of one thousand volts. Alternatively, the first voltage domain might be thousands of volts higher than the second voltage domain (or vice-versa). Electrically coupling the two circuits might result in a loss of signal and/or data integrity and, in some examples, may cause damage to one or more of the circuits. To enable communications, the circuits may be connected in an isolated fashion using, for example, optical isolation, magnetic isolation, capacitive isolation, etc.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an isometric view of a first die and a second die connected via two bond wires.

FIG. 2 is a side view of the first stack of FIG. 1.

FIG. 3 is a top view of the first stack of FIGS. 1 and/or 2.

FIG. 4 is a circuit diagram of the example first die, the example second die, and the example bond wires of FIG. 1.

FIG. 5 is a circuit diagram of the example first die, the example second die, and the example bond wires of FIGS. 1 and/or 4 constructed in accordance with the teachings of this disclosure.

FIG. 6 is a diagram of the example first die, the example second die, the bond wires, and the inductors of FIG. 5.

FIG. 7 is a circuit diagram illustrating an example approach for transmitting and/or driving a signal across the capacitively coupled channels of FIGS. 5 and/or 6.

FIG. 8 is a magnitude plot illustrating magnitudes of example received signals across a frequency spectrum.

The figures are not to scale. Instead, to clarify multiple layers and regions, the thickness of the layers may be enlarged in the drawings. Wherever possible, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts. As used in this patent, stating that any part (e.g., a layer, film, area, or plate) is in any way positioned on (e.g., positioned on, located on, disposed on, or formed on, etc.) another part, means that the referenced part is either in contact with the other part, or that the referenced part is above the other part with one or more intermediate part(s) located therebetween. Stating that any part is in contact with another part means that there is no intermediate part between the two parts.

DETAILED DESCRIPTION

Digital isolation of signals is an emerging technology. Two main technologies for digital isolation are transformers and isolation capacitors. Currently, isolation capacitor approaches require large power draws to operate amplifiers that enhance signal quality. Example approaches disclosed herein utilize inductors within the isolation capacitor circuit to achieve passive gain, which has a much lower power requirement than prior active amplification approaches.

In examples disclosed herein, both a primary side of the isolation circuit and a secondary side of the isolation circuit are tuned for passive gain. In some examples, the gain at a desired frequency can be three to four times the attenuated signal (or any other gain value), depending on the selected value(s) of the inductors, without requiring any current for active amplification. Tuning both a primary side (e.g., a transmit side) and a secondary side (e.g., a receive side) to a same frequency increases Common Mode Transient Immunity (CMTI) and Ground Noise Transient Immunity (GNTI) performance of the isolation system. In some examples, using an input signal frequency (e.g., a modulation frequency) that matches the tuned frequency of the transmit and receive sides further increases Common Mode Transient Immunity (CMTI) and Ground Noise Transient Immunity (GNTI) performance of the isolation system.

FIG. 1 is an isometric view of a communication system 100 including a first die 102 and a second die 104 connected via two bond wires 106, 108. The example isometric view of the illustrated example of FIG. 1 uses a scale 109 of 1 millimeter (mm). However, any other scale may additionally or alternatively be used. In the illustrated example of FIG. 1, the first example die 102 includes a first stack 110 and a second stack 115. The first example die 102 includes a first substrate 117. In the illustrated example of FIG. 1, the second example die 104 includes a third stack 120 and a fourth stack 125. The second example die 104 includes a second substrate 127.

In the illustrated example of FIG. 1, the first example bond wire 106 couples the first stack 110 and the third stack 120. In the illustrated example of FIG. 1, the second example bond wire 108 couples the second stack 115 and the fourth stack 125.

In the illustrated example of FIG. 1, the first example die 102 represents a transmit side of the example communication system 100 of FIG. 1. The second example die 104 represents a receive side of the example communication system 100 of FIG. 1. In the illustrated example of FIG. 1, the communication system 100 is represented as a unidirectional communication system that communicates from the first die 102 to the second die 104 via the bond wires 106, 108. However, in some examples, a bi-directional communication system may be implemented. In such examples, additional bond wires and/or stacks may be used to facilitate communication in both directions.

FIG. 2 is a side view of the first stack 110 of FIG. 1. While the illustrated example of FIG. 2 is described in connection with the first stack 110 of FIG. 1, the example of FIG. 2 is also applicable to the second stack 115, the third stack 120, and the fourth stack 125 of FIG. 1. In the illustrated example of FIG. 2, the stack 110 includes a top plate 205 and a bottom plate 210. The bottom plate 210 is positioned intermediate the top plate 205 and the first substrate 117 (or the second substrate 127). In the illustrated example of FIG. 2, the top plate 205 and the bottom plate 210 are arranged substantially parallel to each other. In the illustrated example of FIG. 2, the top plate 205 and the bottom plate 210 are arranged substantially parallel to the substrate 117. As used herein, the plates and substrate are substantially parallel when a distance between the top plate 205 and the bottom plate 210, between the top plate 205 and the substrate 117, and/or between the bottom plate 210 and the substrate does not deviate from the average distance by more than twenty percent.

A first capacitance 215 is created between the top plate 205 and the bottom plate 210. A second capacitance 220 is created between the bottom plate 210 and the substrate. In the illustrated example of FIG. 2, the top plate 105 is connected to a bond wire 225 (e.g., the first bond wire 106, the second bond wire 108). In examples disclosed herein, the bottom plate 210 receives an input electrical signal.

In the illustrated example of FIG. 2, the top plate 205 and the bottom plate 210 are encased in a dielectric 230. That is, the dielectric 230 surrounds both the top plate 205 and the bottom plate 210 and is in contact with the substrate 117. In some examples, the dielectric 230 surrounds the substrate 117. In some examples, the same dielectric is used for an entire die. That is, the dielectric of the first die 102 of FIG. 2 may encase a top plate and a bottom plate of the first stack 110, as well as a top plate and a bottom plate of the second stack 115. In examples disclosed herein, the dielectric 230 is silicon dioxide. However, any other dielectric material may additionally or alternatively be used.

FIG. 3 is a top view of the first stack 110 of FIG. 1. While the illustrated example of FIG. 3 is described in connection with the first stack 110 of FIG. 1, the example of FIG. 3 is also applicable to the second stack 115, the third stack 120, and the fourth stack 125 of FIG. 1. In the illustrated example of FIG. 3, the top plate 205 has a surface area smaller than the bottom plate 210. The bottom plate 210 has a surface area smaller than the substrate 117. As a result of the difference in surface area and/or the spacing between the top plate 205 and the bottom plate 210, the capacitances 215, 220 are different. The example view 300 of the illustrated example of FIG. 3 represents the first stack 110 of FIG. 1. However, the second stack 115, the third stack 120, and the fourth stack 125 may be arranged in a similar fashion.

In implementation, it is desirable to have the sizes of the top plates match in size among the first stack 110, the second stack 115, the third stack 120, and the fourth stack 125. Likewise, it is desirable to have the sizes of the bottom plates match in size among the first stack 110, the second stack 115, the third stack 120, and the fourth stack 125. Using matching plate sizes ensures that the capacitances formed between the substrates and the plates match between each of the first stack 110, the second stack 115, the third stack 120, and the fourth stack 125.

FIG. 4 is a circuit diagram 400 of the example first die 102, the example second die 104, and the example bond wires 106, 108 of FIG. 1. In the illustrated example of FIG. 4, the example first die 102 includes a first capacitance 402, a second capacitance 406, a first resistance 408, a second resistance 410, a third capacitance 412, and a fourth capacitance 416. In the illustrated example of FIG. 4, four nodes 401, 404, 414, 419 are represented within the first example die 102. In the illustrated example of FIG. 4, the first node 401 represents a first top plate of the first die 102 (e.g., the top plate of the first stack 110 FIG. 1). The second example node 404 represents a first bottom plate of the first die 102 (e.g., the bottom plate of the first stack 110 of FIG. 1). The third example node 414 represents a second bottom plate of the first die 102 (e.g., the bottom plate of the second stack 115 of FIG. 1). The fourth example node 419 represents a second top plate of the first die 102 (e.g., the top plate of the second stack 115 of FIG. 1).

In the illustrated example of FIG. 4, the first capacitance 402 represents a capacitance formed between the first node 401 and the second node 404 (e.g., between the top and bottom plates of the first stack 110 of FIG. 1). The second capacitance 406 represents a capacitance formed between the second node 404 and a substrate of the first die 102 (e.g., a capacitance formed between the bottom plate of the first stack 110 FIG. 1 and the substrate 117 of FIG. 1). The first resistance 408 represents a resistance of the substrate. Thus, the first resistance 408 models losses experienced at the substrate.

In the illustrated example of FIG. 1, the second resistance 410 represents a resistance of the substrate (e.g., the second resistance 410 models losses experienced at the substrate). The third capacitance 412 represents capacitance formed between the substrate of the first die 102 and the third node 414 (e.g., between the substrate 117 and the bottom plate of the second stack 115 of FIG. 1). The fourth example capacitance 416 represents capacitance formed between the third node 414 and the fourth node 419 (e.g., between the bottom plate of the second stack 115 and the top plate of the second stack 115 of FIG. 1).

In the illustrated example of FIG. 4, the example second die 104 includes a fifth capacitance 422, a sixth capacitance 426, a third resistance 428, a fourth resistance 430, a seventh capacitance 432, and an eighth capacitance 436. In the illustrated example of FIG. 4, four nodes 421, 424, 434, 439 are represented within the second example die 104. In the illustrated example of FIG. 4, the fifth node 422 represents a first top plate of the second die 104 (e.g., the top plate of the third stack 120 FIG. 1). The sixth example node 424 represents a first bottom plate of the second die 104 (e.g., the bottom plate of the third stack 120 of FIG. 1). The seventh example node 434 represents a second bottom plate of the second die 104 (e.g., the bottom plate of the fourth stack 125 of FIG. 1). The eighth example node 439 represents a second top plate of the second die 104 (e.g., the top plate of the fourth stack 120 of FIG. 1).

In the illustrated example of FIG. 4, the fifth capacitance 422 represents a capacitance formed between the fifth node 421 and the sixth node 424 (e.g., between the top and bottom plates of the third stack 120 of FIG. 1). The sixth capacitance 426 represents a capacitance formed between the sixth node 424 and a substrate of the second die 104 (e.g., a capacitance formed between the bottom plate of the third stack 120 FIG. 1 and the substrate 127 of FIG. 1). The third resistance 428 represents a resistance of the substrate (e.g., the third resistance 428 models losses experienced at the substrate).

In the illustrated example of FIG. 1, the fourth resistance 430 represents a resistance of the substrate (e.g., the fourth resistance 430 models losses experienced at the substrate). The seventh capacitance 432 represents a capacitance formed between the substrate of the first die 102 and the seventh node 434 (e.g., between the substrate 127 and the bottom plate of the fourth stack 125 of FIG. 1). The eighth example capacitance 436 represents a capacitance formed between the seventh node 434 and the eighth node 439 (e.g., between the bottom plate of the fourth stack 125 and the top plate of the fourth stack 125 of FIG. 1).

In examples disclosed herein, values for the capacitances and resistances of the first die 102 and the second die 104 are based on the physical arrangement of the substrates and the components of the stacks (e.g., the top plates and the bottom plates). Examples disclosed herein assume that the structure of the first stack 110, the second stack 115, the third stack 120, and the fourth stack 125 are consistent. Thus, the values for the first capacitance 402, the fourth capacitance 416, the fifth capacitance 422 and the eighth capacitance 436 match (and are represented as Ciso in FIG. 5). Likewise, the values for the second capacitance 406, the third capacitance 412, the sixth capacitance 426, and the seventh capacitance 432 match (and are represented as Cbot in FIG. 5). However, in some examples, the structures might not match (intentionally or otherwise), resulting in different values for the capacitances.

In the illustrated example of FIG. 4, a first end of the first bond wire 106 is connected to the first node 401 (e.g., to the top plate of the first stack 110). A second end of the first bond wire 106 is connected to the fifth node 421 (e.g., the top plate of the third stack 120 of FIG. 1). The example first bond wire 106 is represented by a first inductance 442 and a fifth resistance 444.

In the illustrated example of FIG. 4, a first end of the second bond wire 108 is connected to the fourth node 419 (e.g. the top plate of the second stack 115 of FIG. 1). A second end of the second bond wire 108 is connected to the eighth node 439 (e.g., the top plate of the fourth stack 125 of FIG. 1). The example second bond wire 108 is represented by a second inductance 452 and a sixth resistance 454.

In the illustrated example of FIG. 4, a voltage signal is applied across the second node 404 and the third node 414, and is received at the sixth node 424 and the seventh node 434. In examples disclosed herein, the voltage difference between the sixth node 424 and the seventh node 434 is attenuated with respect to the voltage difference between the second node 404 and the third node 414. In some examples, the attenuation of the voltage is a result of losses experienced across isolation capacitances (e.g., the first capacitance 402, the fourth capacitance 416, the fifth capacitance 422, and/or the eighth capacitance 436). In some examples, attenuation is the result of differences between the capacitance formed between the substrate(s) and the bottom plate(s) as compared to the capacitance formed between the bottom plate(s) and the top plate(s). In some examples, attenuation is also the result of parasitic capacitances between the bond wires 106, 108.

To facilitate more reliable signal transmission (e.g., transmission with lower attenuation), some example approaches utilize amplification at the receiving side (e.g., at the second die 104). However, noise is also amplified using this approach. Because noise is also amplified, a signal to noise ratio of the transmission is not improved. An alternative approach utilizes an increased voltage differential at the transmission side (e.g., at the first die 102). However, providing an increased voltage differential is not always feasible, as voltage limits on transistors used to apply the voltage differential across the second and third nodes 404, 414 might exist.

To address the deficiencies of existing approaches, inductors are connected between each of the bottom plates of a die. The inductor, in parallel with the capacitances between the bottom plates and the substrate, forms an LC tank that creates a high impedance at a frequency. An example approach using inductors in parallel with the capacitances formed between the bottom plates and the substrate(s) is shown in FIG. 5. FIG. 5 is a circuit diagram of the example first die 102, the example second die 104, and the example bond wires 106, 108 of FIGS. 1 and/or 4 constructed in accordance with the teachings of this disclosure. In the illustrated example of FIG. 5, a third inductor 509 and a fourth inductor 529 are added to the circuit 400 of FIG. 4. In the illustrated example of FIG. 5, the third inductor 509 is included intermediate the second node 404 and the third node 414. The fourth inductor 529 is included intermediate the sixth node 424 and the seventh node 434.

In the illustrated example of FIG. 5, the third inductor 509 is in parallel with the second capacitance 406 and the third capacitance 412. The fourth inductor 529 is in parallel with the sixth capacitance 426 and the seventh capacitance 432. As a result of the parallel relationship, a high impedance is created at a resonant frequency between the sixth example node 424 and the seventh example node 434. The resonant frequency is defined by equation 1, below:

$\begin{matrix} {{frequency} = \frac{1}{\sqrt{\frac{{Cbot}*L}{2}}}} & {{Equation}\mspace{14mu} 1} \end{matrix}$

In the example Equation 1, above, Cbot represents the capacitance formed between a bottom plate of a stack (e.g., the first stack 110 of FIG. 1) and the corresponding substrate. L represents the value of the inductor (e.g., the third inductor 509 or the fourth inductor 529). When each of the transmit side (e.g., the first die 102) and the receive side (e.g., the second die 104) are tuned such that their frequencies match, noise is filtered out, thereby improving the signal to noise ratio of the received signal. In some examples, an additional capacitor is added in parallel with one or more of the inductors 509, 529 to facilitate fine tuning of the frequency. Such an approach does not require active amplification and, as a result, does not consume large amounts of power.

FIG. 6 is a diagram of the example first die 102, the example second die 104, the bond wires 106, 108, and the inductors 509, 529 of FIG. 5. In the illustrated example of FIG. 6, the first inductor 509 is connected to a first bottom plate 610 and a second bottom plate 615. The second inductor 529 is connected to a third bottom plate 630 and a fourth bottom plate 635. The first bond wire 106 is connected to a first top plate 620 and a third top plate 640. The second bond wire 108 is connected to a second top plate 625 and a fourth top plate 645.

In the illustrated example of FIG. 6, the inductors 509, 529 are planar inductors. In the illustrated example of FIG. 6, the inductors 509, 529 are arranged in a plane(s) that is/are substantially parallel to a surface of the corresponding substrates 117, 127. As used herein, the inductors are substantially parallel to the surface(s) of the corresponding substrates when a distance between the inductor and the corresponding substrate does not deviate from the average distance between the inductor and the corresponding substrate by more than twenty percent. In some examples, the inductors are encased in the dielectric 230 of FIG. 2. However, any other type of inductor may additionally or alternatively be used. For example, one or more of the inductors may be implemented as an external component (e.g., a discrete component separate from the die 102, 104).

FIG. 7 is a circuit diagram illustrating an example approach for transmitting and/or driving a signal across the capacitively coupled channels of FIGS. 5 and/or 6. In the illustrated example of FIG. 7, a first transistor 705 and a second transistor 710 are added to the circuit 500 of FIG. 5. In the illustrated example of FIG. 7, the first transistor 705 is an n-type metal oxide semiconductor field effect transistor (MOSFET). In some examples, the ground nodes of the first transistor 705 and the second transistor 710 can be connected together and/or connected to a current source. In the illustrated example of FIG. 7, the second transistor 710 is an n-type MOSFET.

A first terminal of the first transistor 705 is connected to ground. A second terminal of the first transistor 705 is connected to the second node 404 (e.g., the bottom plate of the first stack 110). A third terminal of the first transistor 705 is connected to the third node 414 (e.g., the bottom plate of the second stack 115). A first terminal of the second transistor 710 is connected to ground. A second terminal of the second transistor 710 is connected to the third node 414 (e.g., the bottom plate of the second stack 115). A third terminal of the second transistor 710 is connected to the second node 404 (e.g., the bottom plate of the first stack 110).

In the illustrated example of FIG. 7, the first terminal of the first transistor 705 is a source terminal, the second terminal of the first transistor 705 is a drain terminal, and the third terminal of the first transistor 705 is a gate terminal. In the illustrated example of FIG. 7, the first terminal of the second transistor 710 is a source terminal, the second terminal of the second transistor 710 is a drain terminal, and the third terminal of the second transistor 710 is a gate terminal. When arranged in such a fashion, the first and second transistors 705, 710 form an oscillator that oscillates at a frequency defined by Equation 1, above. That is, the frequency of the oscillator matches the tuned frequency of the LC tank. As a result, the oscillation frequency and resonant frequency of the LC tank can be tuned together. In some examples, the frequency can be tuned to a very high value, thereby enabling design of high data rate transmission systems. In implementation, the frequency is typically chosen based on its compatibility with a modulation scheme that is used in the signal to be transmitted.

FIG. 8 is a magnitude plot 800 illustrating magnitudes of example received signals across a frequency spectrum. A horizontal axis 810 of the example plot 800 of FIG. 8 represents a frequency, in GigaHertz (GHz). A vertical axis 820 of the example plot 800 of FIG. 8 represents a magnitude of the received signal, in millivolts (mV). In the illustrated example of FIG. 8, received signals are shown. A first received signal 830 represents a signal received using the circuit 400 of FIG. 4 (e.g., without inductors intermediate the bottom plates of the respective dies.). A second received signal 840 represents a signal received using the circuit 500 of FIG. 5 (e.g., with inductors intermediate the bottom plates of the respective dies). In the illustrated example of FIG. 5, the circuit corresponding to the second received signal 840 is tuned to a resonant frequency of approximately 2.26875 GHz. At 2.26872 GHz, the first received signal 830 has a magnitude of approximately 51 mV, whereas the second received signal 840 has a magnitude of approximately 134 mV. In practice, the resultant values can be different depending upon a number of factors such as, for example, the tuned frequency, the amplitude of the input signal, the gain(s) (Q) of the passive amplifier(s), etc. Thus, as a result of the tuning by the addition of the inductors 509, 529, the magnitude of the received signal at the tuned frequency is larger than it would have otherwise been. As a result, signal transmission over a capacitively isolated connection is made more reliable.

From the foregoing, it will be appreciated that the above disclosed apparatus and articles of manufacture enable transmission of a voltage differential signal using a capacitive coupling. In examples disclosed herein, the inclusion of an inductor intermediate bottom plates of a stacked capacitive coupling system creates an LC tank that operates as a passive amplifier. This passive amplification can be tuned to a desired frequency and, when data is transmitted at that frequency, a signal to noise ratio of the resultant data transfer is increased.

Although certain example methods, apparatus and articles of manufacture have been disclosed herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all methods, apparatus and articles of manufacture fairly falling within the scope of the claims of this patent. 

What is claimed is:
 1. A circuit comprising: a substrate; a first plate substantially parallel to the substrate, thereby forming a first capacitance intermediate the first plate and the substrate; a second plate substantially parallel to the substrate and the first plate, the first plate intermediate the substrate and the second plate; a third plate substantially parallel to the substrate, thereby forming a second capacitance intermediate the third plate and the substrate; a fourth plate substantially parallel to the substrate and the third plate, the third plate intermediate the substrate and the fourth plate; and an inductor connected to the first plate and the third plate, the inductor to, in combination with the first capacitance and the second capacitance, form an LC amplifier.
 2. The circuit of claim 1, wherein the inductor is a planar inductor.
 3. The circuit of claim 2, wherein the planar inductor is substantially parallel to the substrate.
 4. The circuit of claim 1, wherein a first surface area of the first plate is smaller than a second surface area of the substrate.
 5. The circuit of claim 4, wherein a third surface area of the second plate is smaller than the first surface area of the first plate.
 6. The circuit of claim 1, wherein the first plate is separated from the substrate by a first distance and the third plate is separated from the substrate by the first distance.
 7. The circuit of claim 6, wherein the second plate is separated from the first plate by a second distance and the fourth plate is separated from the third plate by the second distance.
 8. The circuit of claim 1, wherein the first plate, the second plate, the third plate, and the fourth plate are encased in a dielectric.
 9. The circuit of claim 1, further including: a first transistor having a first terminal connected to the first plate and a second terminal connected to the third plate; and a second transistor having a third terminal connected to the third plate and a fourth terminal connected to the first plate, the first transistor and the second transistor forming an oscillator.
 10. The circuit of claim 9, wherein the LC amplifier has a peak amplitude at a first frequency, the oscillator is to oscillate at the first frequency.
 11. The circuit of claim 1, further including: a first bond wire connected to the second plate; and a second bond wire connected to the fourth plate, the first plate and the third plate to receive a differential voltage signal for transmission via the first bond wire and the second bond wire.
 12. A system for communication across a capacitively coupled channel, the system comprising: a first die including a first substrate, a first plate, a second plate, a third plate, and a fourth plate, wherein the first plate, the second plate, the third plate, and the fourth plate are substantially parallel to the first substrate, the first plate intermediate the second plate and the first substrate, the third plate intermediate the fourth plate and the first substrate; a first inductor connecting the first plate and the third plate; a second die including a second substrate, a fifth plate, a sixth plate, a seventh plate, and an eighth plate, wherein the fifth plate, the sixth plate, the seventh plate, and the eighth plate are substantially parallel to the second substrate, the fifth plate intermediate the sixth plate and the second substrate, the seventh plate intermediate the eighth plate and the second substrate; a second inductor connecting the fifth plate and the seventh plate; a first bond wire connecting the second plate and the sixth plate; and a second bond wire connecting the fourth plate and the eighth plate.
 13. The system of claim 12, wherein the first inductor is a planar inductor.
 14. The system of claim 13, wherein the planar inductor is substantially parallel to the first substrate.
 15. The system of claim 12, wherein the first plate is separated from the first substrate by a first distance and the third plate is separated from the first substrate by the first distance.
 16. The system of claim 15, wherein the fifth plate is separated from the second substrate by the first distance, and the seventh plate is separated from the second substrate by the first distance.
 17. The system of claim 12, wherein the first plate, the second plate, the third plate, and the fourth plate are encased in a first dielectric.
 18. The system of claim 12, wherein the first die is operated in a first voltage domain and the second die is operated in a second voltage domain different from the first voltage domain.
 19. The system of claim 12, wherein a differential voltage signal is applied across the first plate and the third plate, and is received across the fifth plate and the seventh plate.
 20. A circuit comprising: a substrate; a first plate substantially parallel to the substrate, thereby forming a first capacitance intermediate the first plate and the substrate; a second plate substantially parallel to the substrate and the first plate, the first plate intermediate the substrate and the second plate; an inductor connected to the first plate, the inductor to, in combination with the first capacitance, form an LC amplifier; and a bond wire connected to the second plate. 